Low dropout voltage (LDO) regulators are utilized to generate stable direct current (dc) voltages, for example, in portable, battery-operated devices such as cellular phones, cordless phones, pagers, personal digital assistants, portable personal computers, camcorders, and digital cameras. The demand for low dropout voltage (LDO) regulators has increased in direct proportion to the increased demand for such portable devices.
LDO regulators are characterized by low dropout voltages (i.e., a minimal difference between an unregulated input voltage, such as a voltage received from a battery or transformer, and the regulated (stable) output voltage). An LDO regulator fails to maintain its regulated voltage level (i.e., drops out of regulation) when the unregulated input voltage falls below the regulated output voltage plus the dropout voltage. Thus, by minimizing the dropout voltage, an LDO regulator allows a portable device to operate longer from a single battery charge. That is, the low dropout voltage of the LDO regulator effectively extends the life of the battery by providing a regulated voltage even if the battery is discharged to a value that is within (typically) 100-500 millivolts of the regulated voltage.
FIG. 4 shows a conventional LDO regulator 10 that is connected to a load 50. LDO 10 includes an operational-amplifier (op-amp) 11, a PMOS transistor M, feedback resistors R11 and R12, and a reference voltage supply REF. Load 50 is represented by a resistive load RL and a capacitive load CL. In operation, a voltage supply (not shown) applies an input voltage VIN to one terminal of PMOS transistor M, and a portion of the output signal VOUT supplied to load 50 through PMOS transistor M is fed back by way of the feedback resistor R11 and R12 to the non-inverting input terminal of op-amp 11, which receives a stable reference signal from reference voltage supply REF on its inverting input terminal. In response to the feedback signal and the reference signal, op-amp 11 generates an output signal that controls PMOS transistor M to regulate the output signal VOUT.
A very serious problem associated with conventional LDO regulator 10 is that it is not stable for all capacitive loads CL. Known solutions can stabilize this circuit for values of CL larger than approximately 1 uF. Another restriction associated with this circuit is that capacitive load CL must have a low and very well-defined equivalent series resistance.
A conventional voltage control loop of an LDO regulator has two dominant poles. The first pole is created at the output by the load equivalent resistor and the load capacitor. The second pole is located in the control error amplifier (e.g., op-amp 11). Due to the large loop gain of the system, the closed loop response will become quite under-damped. A way to improve and stabilize the control loop is by adding a zero in the loop gain. One traditional effective method to create such a zero is to insert a resistor in series with the load capacitor. This approach has the drawback that higher frequency disturbances (for instance due to load variations or ripple on the power line) are not effectively reduced. Also, the parasitic series impedance of the load capacitor is usually not very well controlled, unless expensive capacitors are used. Sometimes the zero is created in the control error amplifier, but this usually requires large resistor values, which is counterproductive on silicon real estate.
What is needed is an improved negative feedback amplifier system, such as a low-dropout voltage regulator, that is stable over a large load range, does not degrade the ripple rejection at higher frequencies, and minimizes stability dependence on the parasitic resistor of the output capacitor.